1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and particularly, a NAND type flash memory.
2. Description of the Related Art
In recent years, in order to reduce the unit cost per one bit of data and increase storage capacity in a non-volatile semiconductor memory device such as a NAND type flash memory, a flash memory which stores multi-bit data, that is, a volume of information of more than two-levels of data, in one memory cell has been developed. Four threshold distributions of one memory cell in which two bits of data are stored exist corresponding to four-levels data.
It is generally preferred that the form of the threshold distribution of a memory cell including this NAND type flash memory be sharp and narrow in width considering drops in power supply voltage or variations in manufacture. Consequently, in order to achieve this, a step-up width of a programming voltage Vpgm is made to be narrow. However, by narrowing the step-up width of a programming voltage Vpgm, but then the threshold distribution of a memory cell becomes wider by the interference of an adjacent memory cell caused by capacitive coupling of the adjacent cell. With miniaturization, this effect has become significant.
In addition, by narrowing the step-up width of a programming voltage Vpgm and programming, it is possible to reduce the widening of the threshold distribution. However, when narrowing the step-up width of a programming voltage Vpgm, the number of times the programming voltage Vpgm is applied increases, programming time becomes longer and programming speed is reduced. Japanese Laid Open Patent 2005-267687, Japanese Laid Open Patent 2005-267821, Japanese Laid Open Patent 2004-152405, and Japanese Laid Open Patent 2004-327865 are used as reference.